With increased levels of integration of integrated circuits, it is possible to pack more and more functions into a single chip. A power-on-reset circuit is an indispensable component of System-on-Chip (SOC) applications, which provides a reset signal to a variety of digital circuit devices, so that they can start in a controlled manner during the ramp-up of the power supply voltage. In the initial stage of a system initialization, the various digital circuit devices in the SOC must be maintained stable when the power supply voltage ramps up to its final stable value. A power-on reset circuit provides a reset signal within the SOC to ensure that the system can start in a controlled manner. In the normal system operation phase, if the power supply voltage is too low, the power-on-reset circuit automatically generates a low logic level signal for the system until the supply voltage reaches its nominal operating condition, then the power-on-reset circuit will quickly provide a high logic level signal.
FIG. 1 shows a simplified block diagram of a conventional power-on-reset circuit, as known in the prior art. As shown in FIG. 1, the power-on-reset circuit includes a resistor R having a terminal connected to a supply voltage VDD and another terminal connected to a capacitor C at a node A. The node A is connected to a buffer having a hysteresis, which is configured to remove unwanted oscillation of the reset signal POR around the trip point. The Resistor R and the capacitor C form a simple RC delay circuit to delay the power supply voltage at the input of the buffer. The output POR is a delayed power supply signal which is configured to reset the integrated circuit or SOC. The value of the capacitor C is generally large requiring a large silicon area, thereby increasing the chip cost. The conventional power-on-reset circuit has a constant slew rate without the supply brown-out reset functions.
Since an on-chip power-on-reset circuit is required to support a wide range of different slow rates, brown-out reset, and it also has to meet the robustness, low power and low cost requirements, conventional power-on-reset circuits cannot satisfy all these requirements.
Thus, there is a need to provide a novel power-on-reset circuit and method to overcome the above-described drawbacks.